Semiconductor memory parts must be tested after fabrication to eliminate unrepairable parts and identify parts that can be repaired by use of redundancy circuits. This procedure occurs in a normal process of manufacturing. This testing is time consuming and the test fixtures and equipment used for testing are expensive. In memory parts capable of storing millions of bits, the time and equipment expenses become large portions of the cost of manufacturing. In such parts, every addressable location in the memory array must have a bit written to it and read from it numerous times with many different data patterns to ascertain that the part operates correctly.
Semiconductor memory parts generally and dynamic random access memories (DRAMs), in particular, often contain a large array of memory cells subdivided into several separate, equally sized and internally addressable subarrays of equal size. Dividing the array into subarrays facilitates manufacturing the parts. These subarrays of memory cells all have the same or like internal address leads connected to them so that each subarray is accessed in a like manner. The subarrays thus are bitmapped alike.
In order to test Random Access Memory (RAM), it is necessary to apply many different patterns to the internal memory to find any and all defects. These defects are seen when the memory pattern inside the chip is such that the defect causes a memory cell to fail, or one memory cell or cells to interfere with another memory cell or cells. A problem in testing DRAMS requires writing patterns to each array, writing out data and comparing the output to the input to determine if there was an array fail. In chips organized such that each array has its own Input/Output (I/O or DQ) a pattern must be sent to each DQ. In wide DRAMs with many DQs many connections must be made as well as many tests performed.